A 0.3V VDDmin 4+2T SRAM for Searching and In-Memory Computing Using 55nm DDC Technology
نویسندگان
چکیده
منابع مشابه
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias
An SoC with ARM® CortexTM-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted ChannelTM (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively, DDC technology demonstrates 35% speed increase at matched power. The results hold across proc...
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